The present invention relates to a method and/or architecture for improved memory access efficiency generally and, more particularly, to a queue circuit that propagates memory read requests ahead of memory write requests.
Access to memory has always been very important. Often many different subsystems are attempting to read and write from/to a single memory in rapid succession. Writes are not time critical. As long as the data is accepted somewhere, the source of the write can then carry on processing. Reads are however time critical. Usually, when a read is requested, the requester has to stall until the data is made available. If there are lots of writes ahead of the read, it can stall the requesting module for a long time. The motivation is to reduce the time that the read takes to get serviced.
A high speed processor is capable of presenting a new write access request in a single clock cycle. A random access memory commonly requires many clock cycles to accept each write access request. A write First-In-First-Out (FIFO) circuit is commonly positioned between the processor and the memory to solve the timing difference between the processor and the memory.
The write FIFO temporarily stores the write access requests at a speed that matches the processor. The write access requests are stored in order of arrival. The write FIFO presents the stored write access requests to the memory at a speed that matches the memory. The write access requests are presented to the memory in the same order of arrival as received from the processor.
When the processor issues a read access request, then the read access request commonly contends with the write access requests already in the FIFO. As a result, servicing of the read access requests by the memory is delayed until the earlier write access requests are cleared or flushed from the write FIFO. The delay forces the processor to stall and wait as the data associated with the read access request is retrieved from the memory.
The present invention concerns a circuit generally comprising a queue having an input and an output. The queue may be used to buffer memory requests generated by a processor to access a memory. The input may be configured to receive a plurality of memory requests. The memory requests may include a plurality of write requests and a plurality of read requests. The output may be configured to present the memory requests. The queue may be configured to (i) store the memory requests received at the input in an arrival order, (ii) rearrange the memory requests by propagating each read request ahead of each write request to establish a presentation order, and (iii) present the memory requests at the output in the presentation order.
The objects, features and advantages of the present invention include providing a method and/or architecture for improved memory access efficiency generally and, more particularly, to a circuit that may (i) decrease read access request latency to a memory, (ii) avoid stall cycles by a requesting processor, and/or (iii) maintain proper sequencing between a write access request and a later read access request to the same address.